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sen393/README.md
Kevin Zhang

~/projects

  • Pipelined RISC-V CPU — A five-stage RV32I core in SystemVerilog, with custom simulation tests and bounded formal verification. Building toward an FPGA system.
  • Single-Cycle RISC-V CPU — A Verilog processor project covering datapath design, self-checking tests, and FPGA synthesis.

~/about

I'm Kevin, an Electrical and Computer Engineering student at Cornell. I enjoy building digital hardware and figuring out how to prove it works. I am also a design verification engineer at Cornell Custom Silicon Systems (C2S2).

~/contact

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  1. riscv-pipelined-cpu riscv-pipelined-cpu Public

    Five-stage RV32I RISC-V processor implemented in SystemVerilog, featuring pipeline hazard handling, precise exceptions, and bounded architectural verification using riscv-formal.

    SystemVerilog 1

  2. riscv-single-cycle-cpu riscv-single-cycle-cpu Public

    32-bit single-cycle RV32I CPU in Verilog, verified with self-checking tests and implemented on a Spartan-7 FPGA at ~64.7 MHz.

    Verilog 1