Skip to content

RTSS Mailbox for monaco and bootup fix for Agatti #1372

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
Salendarsingh Gaud (sgaud-quic) merged 8 commits into from
Oct 31, 2026
+112 −112
Merged

RTSS Mailbox for monaco and bootup fix for Agatti #1372

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
8 commits
Select commit Hold shift + click to select a range
2a85d16
QCLINUX: arm64: dts: qcom: monaco: Add IPCC, syscon, and memory nodes…
sargarram7 Sep 9, 2026
81a348d
Revert "FROMLIST: arm64: dts: qcom: shikra: Add CPU idle states"
ricardosalveti Oct 31, 2026
a66b743
Revert "FROMLIST: irqchip/irq-qcom-mpm: Program wakeup timer when CPU…
ricardosalveti Oct 31, 2026
d9fd7e2
Revert "FROMLIST: irqchip/irq-qcom-mpm: Prepare common access path fo…
ricardosalveti Oct 31, 2026
d8fb59b
Revert "FROMLIST: irqchip/irq-qcom-mpm: Register MPM under CPU cluste…
ricardosalveti Oct 31, 2026
08f9919
Revert "FROMLIST: dt-bindings: interrupt-controller: mpm: Document po…
ricardosalveti Oct 31, 2026
72a7af8
FROMLIST: irqchip: irq-qcom-mpm: Register MPM with cpu_pm for RPM not…
smankad-oss Oct 27, 2026
3d71e56
FROMLIST: arm64: dts: qcom: shikra: Add CPU idle states
smankad-oss Oct 27, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 3 additions & 3 deletions Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -68,8 +68,8 @@ properties:
- description: MPM pin number
- description: GIC SPI number for the MPM pin

power-domains:
maxItems: 1
'#power-domain-cells':
const: 0

required:
- compatible
Expand Down Expand Up @@ -113,6 +113,6 @@ examples:
<24 79>,
<86 183>,
<91 260>;
power-domains = <&cluster_pd>;
#power-domain-cells = <0>;
};
};
58 changes: 57 additions & 1 deletion arch/arm64/boot/dts/qcom/monaco.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -784,6 +784,21 @@
hwlocks = <&tcsr_mutex 3>;
};

tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
reg = <0x0 0x90c00000 0x0 0x100000>;
no-map;
};

sail_mailbox_mem: sail-ss@90d00000 {
reg = <0x0 0x90d00000 0x0 0x100000>;
no-map;
};

sail_ota_mem: sail-ss@90e00000 {
reg = <0x0 0x90e00000 0x0 0x300000>;
no-map;
};

gunyah_md_mem: gunyah-md-region@91a80000 {
reg = <0x0 0x91a80000 0x0 0x80000>;
no-map;
Expand Down Expand Up @@ -959,6 +974,42 @@
#mbox-cells = <2>;
};

ipcc1: mailbox@488000 {
compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
reg = <0x0 0x00488000 0x0 0x1000>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

ipcc2: mailbox@4a1000 {
compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
reg = <0x0 0x004a1000 0x0 0x1000>;
interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

ipcc3: mailbox@4a2000 {
compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
reg = <0x0 0x004a2000 0x0 0x1000>;
interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

ipcc4: mailbox@4a3000 {
compatible = "qcom,qcs8300-ipcc", "qcom,ipcc";
reg = <0x0 0x004a3000 0x0 0x1000>;
interrupts = <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

qfprom: efuse@784000 {
compatible = "qcom,qcs8300-qfprom", "qcom,qfprom";
reg = <0x0 0x00784000 0x0 0x2410>;
Expand Down Expand Up @@ -2809,7 +2860,7 @@

tcsr: syscon@1fc0000 {
compatible = "qcom,qcs8300-tcsr", "syscon";
reg = <0x0 0x1fc0000 0x0 0x30000>;
reg = <0x0 0x1fc0000 0x0 0x40000>;
};

remoteproc_adsp: remoteproc@3000000 {
Expand Down Expand Up @@ -7525,6 +7576,11 @@
#address-cells = <0>;
};

apsshm_shared_intu: syscon@17c00000 {
compatible = "qcom,qcs8300-apsshm-shared-intu", "syscon";
reg = <0x0 0x17c00000 0x0 0x38>;
};

watchdog@17c10000 {
compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt";
reg = <0x0 0x17c10000 0x0 0x1000>;
Expand Down
9 changes: 4 additions & 5 deletions arch/arm64/boot/dts/qcom/shikra.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -384,25 +384,25 @@
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
domain-idle-states = <&little_cpu_sleep_0>, <&little_cpu_sleep_1>;
};

cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
domain-idle-states = <&little_cpu_sleep_0>, <&little_cpu_sleep_1>;
};

cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
domain-idle-states = <&little_cpu_sleep_0>, <&little_cpu_sleep_1>;
};

cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
domain-idle-states = <&big_cpu_sleep_0>, <&big_cpu_sleep_1>;
};

cluster_pd: power-domain-cluster {
Expand Down Expand Up @@ -530,7 +530,6 @@
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
power-domains = <&cluster_pd>;
qcom,mpm-pin-count = <96>;
qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */
<12 422>, /* DWC3 ss_phy_irq */
Expand Down
Loading
Loading