Repository navigation
arm64: dts: qcom: monaco-evk-staging: fix missing Ethernet interfaces - #2161
Eshitha oyyavuru (kppeoyyavuru) wants to merge 1 commit into
Conversation
|
Dev Completion validation failed CR: 4717834 The change task for this CR could not be moved to Dev Complete because of the error above. Please resolve the issue in Orbit and re-run the failed Orbit check. |
PR #2161 — validate-patchPR: #2161
Final Summary
|
PR #2161 — checker-log-analyzerPR: #2161
Detailed report: Full report
|
577a428 to
282c59f
Compare
PR #2161 — validate-patchPR: #2161
Final Summary
|
PR #2161 — checker-log-analyzerPR: #2161
Detailed report: Full report
|
282c59f to
23bbdf6
Compare
PR #2161 — validate-patchPR: #2161
Final Summary
|
PR #2161 — checker-log-analyzerPR: #2161
Detailed report: Full report
|
…nterfaces On some boards, the MDIO bus fails to discover the PHY because it returns no valid reset values. Port 0 uses an AQR113C PHY with its active-low RST_N pin connected to a TLMM GPIO. Configure the reset GPIO with the correct polarity so the PHY is reset before MDIO discovery. PHY discovery then succeeds on both the affected boards and the boards that were already working. Signed-off-by: Eshitha Oyyavuru <eoyyavur@qti.qualcomm.com>
23bbdf6 to
cfe6783
Compare
PR #2161 — validate-patchPR: #2161
Final Summary
|
PR #2161 — checker-log-analyzerPR: #2161
Detailed report: Full report
|
On some boards, the MDIO bus fails to discover the PHY because the
PHY returns no valid reset values during discovery.
Port 0 uses an AQR113C PHY. Its active-low RST_N pin is connected
to a TLMM GPIO, so the reset GPIO needs to be configured with
GPIO_ACTIVE_LOW.
This change applies the correct reset polarity before MDIO discovery.
PHY discovery succeeds on both the previously affected boards and
the boards that were already working.
CRs-Fixed: 4717834
QLIJIRA: QLIJIRA-104