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@OpenXiangShan

XiangShan

Open-source high-performance RISC-V processor

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  1. XiangShan XiangShan Public

    Open-source high-performance RISC-V processor

    Scala 7.3k 963

  2. XiangShan-doc XiangShan-doc Public

    Documentation for XiangShan

    Markdown 447 152

  3. HuanCun HuanCun Public

    Open-source high-performance non-blocking cache

    Scala 101 40

  4. difftest difftest Public

    Modern co-simulation framework for RISC-V CPUs

    C++ 189 111

  5. xs-env xs-env Public

    XiangShan Frontend Develop Environment

    Shell 73 77

  6. NEMU NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    C 352 147

Repositories

Showing 10 of 111 repositories
  • AME_spike Public
    OpenXiangShan/AME_spike's past year of commit activity
    C 44 4 0 0 Updated Oct 16, 2026
  • xsai-env Public Forked from OpenXiangShan/xs-env

    XSAI Frontend Develop Environment

    OpenXiangShan/xsai-env's past year of commit activity
    Shell 0 77 0 0 Updated Oct 16, 2026
  • bootcamp Public

    XiangShan bootcamp

    OpenXiangShan/bootcamp's past year of commit activity
    Jupyter Notebook 7 CC-BY-4.0 4 0 0 Updated Oct 16, 2026
  • XiangShan Public

    Open-source high-performance RISC-V processor

    OpenXiangShan/XiangShan's past year of commit activity
    Scala 7,317 MulanPSL-2.0 963 144 184 Updated Oct 16, 2026
  • AME_gem5 Public
    OpenXiangShan/AME_gem5's past year of commit activity
    C++ 53 BSD-3-Clause 6 0 0 Updated Oct 16, 2026
  • GEM5 Public
    OpenXiangShan/GEM5's past year of commit activity
    C++ 166 BSD-3-Clause 96 18 108 Updated Oct 16, 2026
  • XSAI Public Forked from OpenXiangShan/XiangShan

    A fork of Xiangshan for AI

    OpenXiangShan/XSAI's past year of commit activity
    Scala 62 MulanPSL-2.0 989 4 2 Updated Oct 16, 2026
  • YunSuan Public

    This repo includes XiangShan's function units

    OpenXiangShan/YunSuan's past year of commit activity
    Scala 35 MulanPSL-2.0 22 4 3 Updated Oct 16, 2026
  • NEMU Public

    Super fast RISC-V ISA emulator for XiangShan processor

    OpenXiangShan/NEMU's past year of commit activity
    C 352 147 40 44 Updated Oct 16, 2026
  • XSCache Public

    Open-source L2 (RN) & LLC (HN) cache for XiangShan open-source RISC-V core. Supports CHI Issue B/C/E.b protocols.

    OpenXiangShan/XSCache's past year of commit activity
    Scala 3 8 0 9 Updated Oct 16, 2026