Open-source high-performance RISC-V processor
Scala 7.3k 963
Documentation for XiangShan
Markdown 447 152
Open-source high-performance non-blocking cache
Scala 101 40
Modern co-simulation framework for RISC-V CPUs
C++ 189 111
XiangShan Frontend Develop Environment
Shell 73 77
Super fast RISC-V ISA emulator for XiangShan processor
C 352 147
XSAI Frontend Develop Environment
XiangShan bootcamp
A fork of Xiangshan for AI
This repo includes XiangShan's function units
Open-source L2 (RN) & LLC (HN) cache for XiangShan open-source RISC-V core. Supports CHI Issue B/C/E.b protocols.