diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml index 3f9645fbc3c20..ebb40c48950ab 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml @@ -68,8 +68,8 @@ properties: - description: MPM pin number - description: GIC SPI number for the MPM pin - power-domains: - maxItems: 1 + '#power-domain-cells': + const: 0 required: - compatible @@ -113,6 +113,6 @@ examples: <24 79>, <86 183>, <91 260>; - power-domains = <&cluster_pd>; + #power-domain-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 3d1f3c647425e..e63c5e2848061 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -784,6 +784,21 @@ hwlocks = <&tcsr_mutex 3>; }; + tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { + reg = <0x0 0x90c00000 0x0 0x100000>; + no-map; + }; + + sail_mailbox_mem: sail-ss@90d00000 { + reg = <0x0 0x90d00000 0x0 0x100000>; + no-map; + }; + + sail_ota_mem: sail-ss@90e00000 { + reg = <0x0 0x90e00000 0x0 0x300000>; + no-map; + }; + gunyah_md_mem: gunyah-md-region@91a80000 { reg = <0x0 0x91a80000 0x0 0x80000>; no-map; @@ -959,6 +974,42 @@ #mbox-cells = <2>; }; + ipcc1: mailbox@488000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x00488000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc2: mailbox@4a1000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a1000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc3: mailbox@4a2000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a2000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc4: mailbox@4a3000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a3000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + qfprom: efuse@784000 { compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; reg = <0x0 0x00784000 0x0 0x2410>; @@ -2809,7 +2860,7 @@ tcsr: syscon@1fc0000 { compatible = "qcom,qcs8300-tcsr", "syscon"; - reg = <0x0 0x1fc0000 0x0 0x30000>; + reg = <0x0 0x1fc0000 0x0 0x40000>; }; remoteproc_adsp: remoteproc@3000000 { @@ -7525,6 +7576,11 @@ #address-cells = <0>; }; + apsshm_shared_intu: syscon@17c00000 { + compatible = "qcom,qcs8300-apsshm-shared-intu", "syscon"; + reg = <0x0 0x17c00000 0x0 0x38>; + }; + watchdog@17c10000 { compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt"; reg = <0x0 0x17c10000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index ad76c37e6c4da..1db81afaaa034 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -384,25 +384,25 @@ cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; - domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; + domain-idle-states = <&little_cpu_sleep_0>, <&little_cpu_sleep_1>; }; cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; - domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; + domain-idle-states = <&little_cpu_sleep_0>, <&little_cpu_sleep_1>; }; cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; - domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; + domain-idle-states = <&little_cpu_sleep_0>, <&little_cpu_sleep_1>; }; cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&cluster_pd>; - domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + domain-idle-states = <&big_cpu_sleep_0>, <&big_cpu_sleep_1>; }; cluster_pd: power-domain-cluster { @@ -530,7 +530,6 @@ interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; - power-domains = <&cluster_pd>; qcom,mpm-pin-count = <96>; qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ <12 422>, /* DWC3 ss_phy_irq */ diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c index 2d3460e2aa659..b6caea90e9f41 100644 --- a/drivers/irqchip/irq-qcom-mpm.c +++ b/drivers/irqchip/irq-qcom-mpm.c @@ -4,7 +4,6 @@ * Copyright (c) 2010-2020, The Linux Foundation. All rights reserved. */ -#include #include #include #include @@ -13,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -21,13 +19,10 @@ #include #include #include -#include #include #include #include -#include - /* * This is the driver for Qualcomm MPM (MSM Power Manager) interrupt controller, * which is commonly found on Qualcomm SoCs built on the RPM architecture. @@ -69,23 +64,11 @@ * */ -#define MPM_TIMER_REGS 2 - -enum qcom_mpm_reg { - MPM_REG_TIMER = 0, - MPM_REG_ENABLE, - MPM_REG_FALLING_EDGE, - MPM_REG_RISING_EDGE, - MPM_REG_POLARITY, - MPM_REG_STATUS, -}; - -#define USECS_TO_CYCLES(time_usecs) xloops_to_cycles((time_usecs) * 0x10C7UL) - -static inline unsigned long xloops_to_cycles(u64 xloops) -{ - return (xloops * loops_per_jiffy * HZ) >> 32; -} +#define MPM_REG_ENABLE 0 +#define MPM_REG_FALLING_EDGE 1 +#define MPM_REG_RISING_EDGE 2 +#define MPM_REG_POLARITY 3 +#define MPM_REG_STATUS 4 /* MPM pin map to GIC hwirq */ struct mpm_gic_map { @@ -94,7 +77,6 @@ struct mpm_gic_map { }; struct qcom_mpm_priv { - struct device *dev; void __iomem *base; raw_spinlock_t lock; struct mbox_client mbox_client; @@ -103,41 +85,23 @@ struct qcom_mpm_priv { unsigned int map_cnt; unsigned int reg_stride; struct irq_domain *domain; - struct notifier_block genpd_nb; + struct generic_pm_domain genpd; struct notifier_block mpm_pm; atomic_t cpus_in_pm; }; -static unsigned int qcom_mpm_offset(struct qcom_mpm_priv *priv, enum qcom_mpm_reg reg, - unsigned int index) +static u32 qcom_mpm_read(struct qcom_mpm_priv *priv, unsigned int reg, + unsigned int index) { - unsigned int reg_offset; - - /* - * Per the vMPM register map, TIMER[0..1] starts at register index 0 and all pin-specific - * registers start after the two TIMER regs. Pin-specific register IDs start at - * MPM_REG_ENABLE, so subtract it to convert to a zero-based pin-register group index. - */ - if (reg == MPM_REG_TIMER) - reg_offset = index; - else - reg_offset = MPM_TIMER_REGS + - (reg - MPM_REG_ENABLE) * priv->reg_stride + index; - - return reg_offset * sizeof(u32); -} - -static u32 qcom_mpm_read(struct qcom_mpm_priv *priv, enum qcom_mpm_reg reg, unsigned int index) -{ - unsigned int offset = qcom_mpm_offset(priv, reg, index); + unsigned int offset = (reg * priv->reg_stride + index + 2) * 4; return readl_relaxed(priv->base + offset); } -static void qcom_mpm_write(struct qcom_mpm_priv *priv, enum qcom_mpm_reg reg, +static void qcom_mpm_write(struct qcom_mpm_priv *priv, unsigned int reg, unsigned int index, u32 val) { - unsigned int offset = qcom_mpm_offset(priv, reg, index); + unsigned int offset = (reg * priv->reg_stride + index + 2) * 4; writel_relaxed(val, priv->base + offset); @@ -178,7 +142,7 @@ static void qcom_mpm_unmask(struct irq_data *d) irq_chip_unmask_parent(d); } -static void mpm_set_type(struct qcom_mpm_priv *priv, bool set, enum qcom_mpm_reg reg, +static void mpm_set_type(struct qcom_mpm_priv *priv, bool set, unsigned int reg, unsigned int index, unsigned int shift) { unsigned long flags, val; @@ -331,36 +295,6 @@ static irqreturn_t qcom_mpm_handler(int irq, void *dev_id) return ret; } -static void mpm_write_next_wakeup(struct qcom_mpm_priv *priv) -{ - ktime_t now, wakeup = KTIME_MAX; - u64 wakeup_us, wakeup_cycles = ~0; - u32 lo, hi; - - /* Set highest time when system (timekeeping) is suspended */ - if (system_state == SYSTEM_SUSPEND) - goto exit; - - /* Find the relative wakeup in kernel time scale */ - wakeup = dev_pm_genpd_get_next_hrtimer(priv->dev); - - /* Find the relative wakeup in kernel time scale */ - now = ktime_get(); - wakeup = ktime_sub(wakeup, now); - wakeup_us = ktime_to_us(wakeup); - - /* Convert the wakeup to arch timer scale */ - wakeup_cycles = USECS_TO_CYCLES(wakeup_us); - wakeup_cycles += arch_timer_read_counter(); - -exit: - lo = wakeup_cycles; - hi = wakeup_cycles >> 32; - - qcom_mpm_write(priv, MPM_REG_TIMER, 0, lo); - qcom_mpm_write(priv, MPM_REG_TIMER, 1, hi); -} - static int handle_rpm_notification(struct qcom_mpm_priv *priv) { int i, ret; @@ -373,23 +307,16 @@ static int handle_rpm_notification(struct qcom_mpm_priv *priv) if (ret < 0) return ret; - mpm_write_next_wakeup(priv); mbox_client_txdone(priv->mbox_chan, 0); return 0; } -static int mpm_pd_power_cb(struct notifier_block *nb, unsigned long action, void *d) +static int mpm_pd_power_off(struct generic_pm_domain *genpd) { - struct qcom_mpm_priv *priv = container_of(nb, struct qcom_mpm_priv, - genpd_nb); - - switch (action) { - case GENPD_NOTIFY_PRE_OFF: - if (handle_rpm_notification(priv)) - return NOTIFY_BAD; - } + struct qcom_mpm_priv *priv = container_of(genpd, struct qcom_mpm_priv, + genpd); - return NOTIFY_OK; + return handle_rpm_notification(priv); } static int mpm_cpu_pm_callback(struct notifier_block *nfb, unsigned long action, void *v) @@ -443,6 +370,7 @@ static int qcom_mpm_probe(struct platform_device *pdev, struct device_node *pare struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; struct irq_domain *parent_domain; + struct generic_pm_domain *genpd; struct device_node *msgram_np; struct qcom_mpm_priv *priv; unsigned int pin_cnt; @@ -454,8 +382,6 @@ static int qcom_mpm_probe(struct platform_device *pdev, struct device_node *pare if (!priv) return -ENOMEM; - priv->dev = &pdev->dev; - ret = of_property_read_u32(np, "qcom,mpm-pin-count", &pin_cnt); if (ret) { dev_err(dev, "failed to read qcom,mpm-pin-count: %d\n", ret); @@ -541,6 +467,35 @@ static int qcom_mpm_probe(struct platform_device *pdev, struct device_node *pare return ret; } + if (of_find_property(np, "#power-domain-cells", NULL)) { + genpd = &priv->genpd; + genpd->flags = GENPD_FLAG_IRQ_SAFE; + genpd->power_off = mpm_pd_power_off; + + genpd->name = devm_kasprintf(dev, GFP_KERNEL, "%s", dev_name(dev)); + if (!genpd->name) + return -ENOMEM; + + ret = pm_genpd_init(genpd, NULL, false); + if (ret) { + dev_err(dev, "failed to init genpd: %d\n", ret); + return ret; + } + + ret = of_genpd_add_provider_simple(np, genpd); + if (ret) { + dev_err(dev, "failed to add genpd provider: %d\n", ret); + goto remove_genpd; + } + } else { + priv->mpm_pm.notifier_call = mpm_cpu_pm_callback; + ret = cpu_pm_register_notifier(&priv->mpm_pm); + if (ret) { + dev_err(dev, "failed to register for CPU_PM notifications: %d\n", ret); + return ret; + } + } + parent_domain = irq_find_host(parent); if (!parent_domain) { dev_err(dev, "failed to find MPM parent domain\n"); @@ -564,22 +519,12 @@ static int qcom_mpm_probe(struct platform_device *pdev, struct device_node *pare if (ret) goto remove_domain; - if (of_find_property(np, "power-domains", NULL)) { - devm_pm_runtime_enable(dev); - priv->genpd_nb.notifier_call = mpm_pd_power_cb; - ret = dev_pm_genpd_add_notifier(dev, &priv->genpd_nb); - } else { - priv->mpm_pm.notifier_call = mpm_cpu_pm_callback; - ret = cpu_pm_register_notifier(&priv->mpm_pm); - } - - if (ret) - goto remove_domain; - return 0; remove_domain: irq_domain_remove(priv->domain); +remove_genpd: + pm_genpd_remove(genpd); free_mbox: mbox_free_channel(priv->mbox_chan); return ret;